1. Field of the Invention
The present invention relates generally to semiconductor devices and methods thereof, and more particularly to a phase detection circuit and method thereof and a clock recovery circuit and method thereof.
2. Description of the Related Art
A clock data recovery (CDR) circuit may be used in a receiver of a data transmission system operating at higher speeds (e.g., an optical communication system, a backplane routing system, a chip-to-chip interconnection system, etc.) to provide a clock signal for recovering a digital signal. The CDR circuit may be classified into one of two types of CDR depending on whether the CDR circuit receives a reference clock signal from an external crystal oscillator to provide the clock signal.
In a first type of CDR, if the reference clock signal is received from the external crystal oscillator, an external clock and a clock divider may generate a clock signal having a frequency substantially the same as a frequency of a bit rate of input data.
In a second type of CDR, if the reference clock signal is not received from the external crystal oscillator, a frequency detector may extract frequency information from the input data.
In another example, a half-rate CDR having a bit rate equal to half of a bit rate of the input data may be used to transmit data at higher data rates. If the half-rate CDR is used, a pair of phase-locked loops (PLLs) may generate a half-rate quadrature clock. Alternatively, a single PLL may generate the half-rate quadrature clock. If the pair of PLLs is used, a chip area and/or a power consumption of the half-rate CDR may be higher. If the single PLL is used, a voltage controlled oscillator (VCO) may generate a higher frequency corresponding to the higher data transmission rate and quadrature clocks may be transmitted on a receiving channel at higher frequencies.
As the data rate of the CDR increases, using the single PLL may increase a difficulty in designing a complementary metal oxide semiconductor (CMOS) of a PLL/VCO with lower jitter characteristics. Further, during transmission of the clock signal from the CDR to respective channels, a mismatching and/or a coupling effect among transmission lines may be increased proportional to the frequency of the quadrature clock and a power consumption of a transmission buffer.
Further, an operating speed and/or a data rate of the CDR may be based on a phase detector (PD). The PD may operate at higher speeds in order to detect a phase difference between the input data and the clock signal. The phase detector may include a nonlinear PD and a linear PD. The nonlinear PD may detect whether the phase of the clock signal may trail (e.g., be behind) or follow (e.g., be ahead) relative to the phase of the input data. In an example, a CDR may include a quarter-rate binary phase detector and may operate at a data rate of 40 Gbits/sec.
The linear PD may detect a phase error of the clock signal based on the input data. In an example, a CMOS CDR may include a half-rate linear PD and may operate at a data rate of 40 Gbits/s. Relative to the nonlinear PD, the linear PD may cause a lower amount of charge pump activity, a lower ripple on a control voltage of the VCO, and thereby a lower amount of jitter.
The phase detector may include a differential exclusive logic circuit to detect an error signal corresponding to a phase difference between the input data and the clock signal. The detected error signal may have a pulse width narrower than a unit interval (UI).
As the data rate of the input signal applied to the phase detector using the differential exclusive logic circuit increases (e.g., up to 10 Gb/s), a pulse width of the error signal may be decreased (e.g., from 100 picoseconds (ps) to several picoseconds) such that the differential exclusive logic circuit may not detect the error signal. Thus, an operation speed of the differential exclusive logic circuit may act as a “bottleneck” which may limit an operation speed or data rate of the CDR.